As the number of components contained in an integrated circuit increases, such circuits become harder and harder to create with conventional photolithographic printing systems. For example, as the sizes of individual components defined by a mask or reticle become smaller than the wavelength of light used to expose the mask onto a semiconductor wafer, distortions can occur whereby the component pattern created on a wafer does not match the component pattern on the mask. To correct this, numerous resolution enhancement techniques such as optical and process correction (OPC) attempt to compensate for the expected distortions so that the pattern of features created on a wafer will match the desired pattern.
In order to accurately perform OPC and other resolution enhancement techniques, it is necessary to be able to predict how a pattern of features will be printed on a wafer. Therefore, it is necessary to have an accurate model of how the optics of a photolithographic system behave, as well as how the photo-sensitive chemicals, i.e., the resist layers of a wafer will react when exposed using a pattern of features on a mask or reticle. In general, the optics of a photolithographic printing system are independent of the particular circuit pattern to be created on a wafer, and the basic principles of optical modeling techniques have been well established for over a century. Therefore, models can be developed that simulate the optical behavior with a high degree of accuracy. However, the behavior of the photoresist or other processing steps can vary, depending on the particular pattern features that are to be created on a wafer. Therefore, to simulate the resist behavior accurately, it is necessary to calibrate a resist model using a test pattern that represents features similar to the integrated circuit pattern to be created. In the past, it has been difficult to ensure that the test mask pattern accurately represents all the typical features in the integrated circuit to be printed with the calibrated resist model. Therefore, there is a need for a system that allows a user to determine if a test mask pattern will provide an adequate resist model calibration for a desired integrated circuit layout.